1. Field of the Invention
The present invention relates to structures of the back-illuminated, pin photodiode arrays manufactured on thin wafers and methods of manufacturing the same.
2. Prior Art
The structures described herein can be considered an alternative to the conventional structures described previously in U.S. Pat. Nos. 6,762,473 and 7,112,465, as well as in the number of patents from other inventors. See for example U.S. Pat. Nos. 6,933,489, 6,426,991 and 6,707,046.
Pin photodiode arrays for imaging applications are 2D arrays combining multiple pixels separated from each other in one of various different ways. A typical die layout (front view) for the 2D backlit pin photodiode array with isolation diffusion between pixels on the front side is shown in FIG. 1.
In conventional backlit arrays, isolation structures are not usually made on the backside of the array. The example of the vertical structure of such conventional backlit pin photodiode array is shown in FIG. 2. The substrate 1 is a first conductivity type. The active pixel diffusion 100 is of the second conductivity type (polarity is different from that of the substrate). Diffusions 100 form diodes (either p-on-n or n-on p polarity) with p-n junctions in the substrate. The diffusion 101 between pixels is of the same conductivity type as the substrate (the first conductivity type). The diffusions 100 and 101 are usually shallow. The shallow blanket diffusion 5 is of the first conductivity type. Oxide layer 11 is a thermal oxide or other passivation layer. The anode pads 20 and cathode pads 21 complete the structure.
FIG. 3 shows an example of the structure for backlit pin photodiode arrays with isolation diffusion applied from both sides of the wafer (see also U.S. Pat. Nos. 6,762,473 and 7,112,465). In addition to the structure shown in FIG. 3, an additional feature—the isolation diffusion 102 from the backside is applied. The diffusion 102 is of the first conductivity type and is aligned with the diffusion 101 and other structural features on the front side. The diffusions 101 and 102 may or may not meet in the bulk of the wafer. The diffusion 100 may be shallow or as deep as the diffusion 101.
The structure shown in FIG. 3 is characterized with superior performance parameters, such as leakage current, crosstalk between active pixels of the array, response time, and others.